1. Field of the Invention
Example embodiments relate to a fuse circuit, and more particularly a fuse circuit configured to correct errors that occur when programming the fuse circuit and normally generate a fuse signal.
2. Description of the Related Art
Integrated circuits typically include a fuse circuit which includes a fuse capable of being programmed to change an internal setting without changing a design. Electrical connection characteristics of the fuse used in the fuse circuit is changed when a laser beam or an electrical stress is applied to the fuse, and information regarding internal settings of the integrated circuit is programmed using such a change in the electrical connection state of the fuse.
Fuse programming methods are divided into a method of disconnecting the connection state of a fuse using a laser beam, and a method of changing the electrical connection state of a fuse by applying an electrical stress. Fuses programmed using electrical stress (an electrical way) are divided into an anti-type fuse in which electrical connection state is changed from an open state to a short state, and a blowing type fuse in which an electrical connection state is changed from a short state to an open state.
FIG. 1 is a block diagram showing a configuration of a conventional fuse circuit.
Referring to FIG. 1, the conventional fuse circuit includes a programming pulse generation unit 8 configured to receive a programming enable signal PGMEN and first to seventh addresses ADD<1:7> and generate first to eighth pulses P<1:8>, and a fuse unit 9 including first to eighth fuse sections 9(1:8) configured to be programmed in response to the first to eighth pulses P<1:8> and generate first to eighth fuse signals FUSE<1:8>. The first to eighth fuse sections 9(1:8) are realized as fuses which are programmed in an electrical way in response to the first to eighth pulses P<1:8>.
In the fuse circuit configured in this way, the first to eighth fuse sections 9(1:8) are programmed according to the programming enable signal PGMEN and the first to seventh addresses ADD<1:7> and generate the first to eighth fuse signals FUSE<1:8>. For example, assuming that the first to third addresses ADD<1:3> are inputted at a logic high level and the fourth to seventh addresses ADD<4:7> are inputted at a logic low level in a state in which the programming enable signal PGMEN is enabled to a logic high level, the programming pulse generation unit 8 generates the first to fourth pulses P<1:4> of a logic high level and the fifth to eighth pulses P<5:8> of a logic low level. The first to fourth fuse sections 9(1:4) are changed in their electrical connection states according to the programming enable signal PGMEN of the logic high level and the first to third addresses ADD<1:3> of the logic high level and generate the first to fourth fuse signals FUSE<1:4> of a logic high level, and the fifth to eighth fuse sections 9(5:8) generate the fifth to eighth fuse signals FUSE<5:8> of a logic low level.
However, when a fail occurs, for example in the gate dielectric layer in the fifth fuse section 9(5) included in the fuse unit 9, the fifth fuse section 9(5) erroneously generates the fifth fuse signal FUSE<5> at a logic high level instead of the logic low level. As a consequence, an error may occur in the operation of the integrated circuit.